Wei Bing Koh | weibingkoh.com | weibkoh@gmail.com | (734)546-2759
1402 Cottlestone Ct, San Jose , CA 95121
Senior SOC Design Engineer III @ NVIDIA Corp.
Jan 2009 – Present
SOCD Lead/Co-Lead for 3 projects. Manage RTL team coordination during RTL snap to keep to chip schedule; Perform IP level integration, manage SOC integration efforts, and lead project team to successful SOC delivery.
Developed new feedthrough and physical pinning implementation from conception to delivery to deliver accurate pinning in RTL quickly.
Designer of ASIC block to combine inputs and switch between display/usb drivers; Enables Display over USB-C feature.
Managed STA/timing closure for several partitions in Volta project. Performed ECO to make setup/hold fixes; Managed nightly timing spins to check for new timing and netlist check violations.
Responsible for SOC integration of new JTAG controller logic; Coordinate SOC team effort for new DFT features in RTL. Primary SoC contact for microarchitectural consulting from the DFT team regarding feasibility of new features.
Perform ASIC Bringup on GF117. Debug ASIC features and ASIC checklist checkout from day 1 to product sampling.
Developed a task management tool to automate RTL build, synthesis, and post-synthesis tasks.
Synthesis Lead for multiple Fermi and Kepler class chips. Coordinate RTL team synthesis deliverables including netlists, synthesis timing violations, netlist quality checks and formality.
Proficient in:
Verilog|Perl|Python|C|C++|Unix|Shell|TCL|Makefile|Makeppfile
Tools Used :
Design Compiler|Spyglass|VCS|Siloti|Verdi|Formality|Primetime
Skills and Experience:
RTL Design | SoC Design | Timing Closure | Synthesis | Formality | Chip Bringup
Masters of Science in Engineering (Electrical Engineering)
University of Michigan
Class of 2008
Bachelors of Science in Engineering in (Electrical Engineering)
University of Michigan
Class of 2007
Summa Cum Laude